1. Field of the Invention
The present invention relates to a connection device, and more particularly, to a connection device capable of converting a pixel clock to a character clock.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram of a prior art connection device 100. A pixel clock generator 130 generates a pixel clock (PCK) having a number of cycles that is an integer multiple of a predetermined number during a predetermined interval and outputs the PCK to a frequency divider 140. The frequency divider 140 generates a character clock (CCK) according to the PCK output by the pixel clock generator 130 and outputs the CCK to a time control module 120. A logic unit 110 controls a second counter 122 of the time control module 120 so that the second counter 122 controls when a control signal (HSync, VSync, etc.) changes its state (from low level L to high level H or from high level H to low level L) based on the CCK output by the frequency divider 140.
Generally, the character clock controls images displayed on a display. A cycle of the character clock spans eight or nine cycles of the pixel clock (1 CCK cycle=8 or 9 PCK cycles). Therefore, the duration of a cycle of the CCK generated by the frequency divider 140 is eight or nine times that of the PCK.
Suppose that a cycle of the CCK corresponds to eight cycles of the PCK. Please refer to FIG. 2. FIG. 2 shows the CCK state and the PCK state during a predetermined interval. A first counter 142 of the frequency divider 140 counts from 0 to 7 (CNT_PCK is from 0 to 7) continuously. When the values of CNT_PCK are 0, 1, 2, and 3, the CCK is at level H. Otherwise, the CCK is at level L. Therefore, a cycle of the CCK spans eight cycles of the PCK, as shown in FIG. 2. In other words, the frequency divider 140 generates the CCK of FIG. 2 according to the PCK and the value of CNT_PCK.
Please refer to FIG. 3. FIG. 3 shows a control signal and the CCK of FIG. 2. In FIG. 3, consider HSync as the control signal. After time T3 ends and when time T1 starts, the display signal rises from level L to level H so that the screen starts to display images. Before the end of time T1, the display signal drops from level H to level L. When time T1 ends, the control signal HSync rises from level L to level H. The control signal drops from level H to level L when time T2 ends. Note that each duration T1, T2 and T3 is an integer multiple of the CCK. The CCK is generated by the frequency divider 140 of FIG. 1, and a cycle of the CCK is eight time that of the PCK. In FIG. 1, the second counter 122 of the time control module 120 controls the time control module 120 to generate the HSync shown in FIG. 3 according to the CCK output by the frequency divider 140. Then the HSync controls the horizontal scanning of the screen. Note that the horizontal scanning controlled by the HSync signal differs among different manufactures and for different resolutions. For instance, the horizontal scanning is controlled by HSync signal dropping from level H to level L or increasing from level L to level H.
Control signals control the scanning of the display or TV screen when images are displayed. The clock unit of the control signals is one cycle of the CCK, which equals eight or nine cycles of the PCK. That is, such control signals only control screens having horizontal resolutions evenly divisible by eight or nine. However, there are TV screens with high resolutions, such as high definition televisions (HDTV). According to the video electronics standards association (VESA), standard resolutions are 2200×1100, 2640×1320, and 2750×1375 pixels. The horizontal resolution of the resolution 2750×1375, i.e. 2750, is not evenly divisible by eight or nine. Therefore, the prior art connection device 100 cannot control such screens.